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http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3573| Title: | A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-selta modulator for low-power high-linearity automotive aensor ASICs |
| Keywords: | Analog-to-cigital converters Σ-Δ modulation Switched-capacitor |
| Publisher: | Institute of Electrical and Electronics Engineers |
| Description: | This paper describes a 0.35-μm CMOS chopper-stabilized switched-capacitor 2-1 cascade ΣΔ modulator for automotive sensor interfaces. The modulator architecture has been selected from an exhaustive comparison among multiple topologies in terms of resolution, speed and
power dissipation. To obtain a better fitting with the characteristics of different sensor outputs, the circuit can be digitally programmed to yield four gain values (x0.5, x1, x2 and x4) and has been designed to operate within the stringent environmental conditions of automotive electronics. In order to relax the amplifier’s dynamic requirements for the different modulator gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The
design of the building blocks is based on a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12MHz and the overall power consumption is 14.7mW from a single 3.3-V supply. Experimental results show an overall dynamic range of 110dB within a 20-kHz signal bandwidth and 113.8dB for signals. These performance features place the reported circuit at the cutting edge of state-of-the-art high-resolution ΣΔ modulators. This work has been supported by the EU ESPRIT IST Project 2001-34283/TAMES-2. |
| URI: | http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3573 |
| Other Identifiers: | IEEE Journal of Solid-State Circuits 40(11): 2246-2264 (2005), November 2005 0018-9200 http://hdl.handle.net/10261/3573 10.1109/JSSC.2005.857356 |
| Appears in Collections: | Digital Csic |
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