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http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3741| Title: | Clock jitter error in multi-bit continuous-time sigma-delta modulators with non-return-to-zero feedback waveform |
| Keywords: | Analog-to-digital conversion Continuous-time ΣΔ modulation Clock jitter |
| Publisher: | Elsevier |
| Description: | This paper presents a detailed study of the clock jitter error in multi-bit continuous-time ΣΔ modulators with non-return-to-zero feedback waveform. It is demonstrated that jitter-induced noise power can be separated into two main components: one that depends on the modulator loop filter transfer function and the other dependent on input signal parameters, i.e. amplitude and frequency. The latter component, not considered in previous approaches, allows us accurately to predict the resolution loss caused by jitter, showing effects not taken into account previously in literature despite the fact that they are especially critical in broadband telecom applications. Moreover, the use of state-space formulation makes the analysis quite general and applicable to either cascade or single-loop architectures. Closed-form expressions are derived for in-band error power and signal-to-noise ratio that can be used to optimize modulator performance in terms of jitter insensitivity. Time-domain simulations of several modulator topologies (both single-loop and cascade) intended for VDSL application demonstrate the validity of the presented approach. This work has been supported by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under contract TEC2004-01752/MIC. Peer reviewed |
| URI: | http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3741 |
| Other Identifiers: | Microelectronics Journal 39(1): 137-151 (2008) 0026-2692 http://hdl.handle.net/10261/3741 10.1016/j.mejo.2007.10.005 |
| Appears in Collections: | Digital Csic |
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