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http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3743Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.creator | Medeiro, Fernando | - |
| dc.creator | Pérez-Verdú, Belén | - |
| dc.creator | Rosa, José M. de la | - |
| dc.creator | Rodríguez-Vázquez, Ángel | - |
| dc.date | 2008-04-25T10:23:12Z | - |
| dc.date | 2008-04-25T10:23:12Z | - |
| dc.date | 1998-03 | - |
| dc.date.accessioned | 2017-01-31T01:03:48Z | - |
| dc.date.available | 2017-01-31T01:03:48Z | - |
| dc.identifier | Electronics Letters 34(5): 422-424 (1998) | - |
| dc.identifier | 0013-5194 | - |
| dc.identifier | http://hdl.handle.net/10261/3743 | - |
| dc.identifier | 10.1049/el:19980270 | - |
| dc.identifier | 1350-911X | - |
| dc.identifier.uri | http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3743 | - |
| dc.description | El pdf del artículo es la versión post-print. | - |
| dc.description | This paper presents a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantization in a cascade architecture to obtain high resolution with low oversampling ratio. It is less sensitive to the non-linearity of the DAC than those previously reported, thus enabling the use of very simple analog circuitry with neither calibration nor trimming required. | - |
| dc.description | This work has been supported by Spanish C.I.C.Y.T. under contract TIC97-0580. | - |
| dc.description | Peer reviewed | - |
| dc.format | 1193393 bytes | - |
| dc.format | application/pdf | - |
| dc.language | eng | - |
| dc.publisher | Institute of Electrical and Electronics Engineers | - |
| dc.relation | Postprint | - |
| dc.relation | http://dx.doi.org/10.1049/el:19980270 | - |
| dc.rights | openAccess | - |
| dc.subject | Multi-bit ΣΔ modulator | - |
| dc.subject | High-speed ADC | - |
| dc.title | Multi-bit cascade ΣΔ modulator for high-speed A/D conversion with reduced sensitivity to DAC errors | - |
| dc.type | Artículo | - |
| Appears in Collections: | Digital Csic | |
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