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http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3743| Title: | Multi-bit cascade ΣΔ modulator for high-speed A/D conversion with reduced sensitivity to DAC errors |
| Keywords: | Multi-bit ΣΔ modulator High-speed ADC |
| Publisher: | Institute of Electrical and Electronics Engineers |
| Description: | El pdf del artículo es la versión post-print. This paper presents a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantization in a cascade architecture to obtain high resolution with low oversampling ratio. It is less sensitive to the non-linearity of the DAC than those previously reported, thus enabling the use of very simple analog circuitry with neither calibration nor trimming required. This work has been supported by Spanish C.I.C.Y.T. under contract TIC97-0580. Peer reviewed |
| URI: | http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3743 |
| Other Identifiers: | Electronics Letters 34(5): 422-424 (1998) 0013-5194 http://hdl.handle.net/10261/3743 10.1049/el:19980270 1350-911X |
| Appears in Collections: | Digital Csic |
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