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http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3751| Title: | CMOS Comparators |
| Keywords: | CMOS Comparators |
| Publisher: | Springer |
| Description: | This chapter first presents an overview of CMOS voltage comparator architectures and circuits. Starting from the identification of the comparator behavior, Section 2 introduces several comparator architectures and circuits. Then, Section 3 assumes these topologies, characterizes high-level attributes, such as static gain, unitary time constant, etc., and analyzes the trade-off for each architecture. Such analysis provides a basis for comparison among architectures. These previous sections of the chapter neglect the influence of circuit dissymmetries. Dissymmetries are covered in Section 4; and new comparator topologies are
presented to overcome the offset caused by dissymmetries. Related high-level trade-offs for these topologies are also studied in this section. This work has been partially supported by the spanish MCyT and the ERDF - Project TIC2001-0929 (ADAVERE), and the European Union Project IST- 2001-34283 (TAMES). The useful comments from Dr. Gustavo Liñán are highly appreciated. Peer reviewed |
| URI: | http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3751 |
| Other Identifiers: | 1-4020-7546-4 http://hdl.handle.net/10261/3751 |
| Appears in Collections: | Digital Csic |
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