Please use this identifier to cite or link to this item: http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3751
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dc.creatorDomínguez-Castro, R.-
dc.creatorRodríguez-Vázquez, Ángel-
dc.creatorRosa, José M. de la-
dc.creatorDelgado-Restituto, Manuel-
dc.creatorMedeiro, Fernando-
dc.date2008-04-26T23:48:23Z-
dc.date2008-04-26T23:48:23Z-
dc.date2003-
dc.date.accessioned2017-01-31T01:03:54Z-
dc.date.available2017-01-31T01:03:54Z-
dc.identifier1-4020-7546-4-
dc.identifierhttp://hdl.handle.net/10261/3751-
dc.identifier.urihttp://dspace.mediu.edu.my:8181/xmlui/handle/10261/3751-
dc.descriptionThis chapter first presents an overview of CMOS voltage comparator architectures and circuits. Starting from the identification of the comparator behavior, Section 2 introduces several comparator architectures and circuits. Then, Section 3 assumes these topologies, characterizes high-level attributes, such as static gain, unitary time constant, etc., and analyzes the trade-off for each architecture. Such analysis provides a basis for comparison among architectures. These previous sections of the chapter neglect the influence of circuit dissymmetries. Dissymmetries are covered in Section 4; and new comparator topologies are presented to overcome the offset caused by dissymmetries. Related high-level trade-offs for these topologies are also studied in this section.-
dc.descriptionThis work has been partially supported by the spanish MCyT and the ERDF - Project TIC2001-0929 (ADAVERE), and the European Union Project IST- 2001-34283 (TAMES). The useful comments from Dr. Gustavo Liñán are highly appreciated.-
dc.descriptionPeer reviewed-
dc.format863347 bytes-
dc.formatapplication/pdf-
dc.languageeng-
dc.publisherSpringer-
dc.relationhttp://www.springer.com/engineering/circuits+%26+systems/book/978-1-4020-7546-9-
dc.rightsclosedAccess-
dc.subjectCMOS Comparators-
dc.titleCMOS Comparators-
dc.typeCapítulo de libro-
Appears in Collections:Digital Csic

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