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http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3779Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.creator | Tortosa, Ramón | - |
| dc.creator | Aceituno, Antonio | - |
| dc.creator | Rosa, José M. de la | - |
| dc.creator | Fernández, Francisco V. | - |
| dc.creator | Rodríguez-Vázquez, Ángel | - |
| dc.date | 2008-04-28T10:05:26Z | - |
| dc.date | 2008-04-28T10:05:26Z | - |
| dc.date | 2006-12 | - |
| dc.date.accessioned | 2017-01-31T01:04:23Z | - |
| dc.date.available | 2017-01-31T01:04:23Z | - |
| dc.identifier | R. Tortosa, A. Aceituno, J. M. de la Rosa, F.V. Fernández and A. Rodríguez-Vázquez: "Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time ΣΔ Modulator". Proc. of the 2006 IFIP International Conference on Very Large Scale Integration (VLSI-SoC), Niza, December 2006. | - |
| dc.identifier | 3-901882-19-7 | - |
| dc.identifier | http://hdl.handle.net/10261/3779 | - |
| dc.identifier.uri | http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3779 | - |
| dc.description | This paper presents the design of a continuous- time multibit cascade 2-2-1 ΣΔ modulator for broadband telecom systems. The modulator architecture has been synthesized directly in the continuous-time domain instead of using a discrete-to-continuous time transformation. This method results in a more efficient modulator in terms of noise shaping, power consumption and sensitivity to circuit element tolerances. The design of the circuit, realized in a 130nm CMOS technology, is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The estimated power consumption is 60mW from a 1.2-V supply voltage when clocked at 240MHz. Simulation results show 80-dB effective resolution within a 20-MHz signal bandwidth. | - |
| dc.description | This work has been supported by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under contract TEC2004-01752/MIC. | - |
| dc.description | Peer reviewed | - |
| dc.format | 634108 bytes | - |
| dc.format | application/pdf | - |
| dc.language | eng | - |
| dc.publisher | Institute of Electrical and Electronics Engineers | - |
| dc.rights | openAccess | - |
| dc.subject | Continuous-Time Circuits | - |
| dc.subject | Sigma-Delta Modulators | - |
| dc.subject | Low-Voltage | - |
| dc.title | Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time ΣΔ Modulator | - |
| dc.type | Artículo | - |
| Appears in Collections: | Digital Csic | |
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