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http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3829| Title: | A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator |
| Keywords: | Continuous-Time Circuits Sigma-Delta Modulators |
| Publisher: | Institute of Electrical and Electronics Engineers |
| Description: | This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade ΣΔ modulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by a
second-order stage, both realized using Gm-C integrators and a 4-bit internal quantizer. Dynamic element matching is included to compensate for the non-linearity of the feedback
digital-to-analog converters. The estimated power consumption is 70 mW from a 1.2-V supply voltage when is clocked at 240MHz. CADENCE-SPECTRE simulations show 12-bit effective resolution within a 20-MHz signal bandwidth. This work has been supported by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under contract TEC2004-01752/MIC. Peer reviewed |
| URI: | http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3829 |
| Other Identifiers: | R. Tortosa-Navas,A. Aceituno, J. M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: "A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator". Proceeding of the 2007 International Symposium on Circuits and Systems (ISCAS), New Orleans, May 2007. 1-4244-0921-7/07 http://hdl.handle.net/10261/3829 |
| Appears in Collections: | Digital Csic |
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