Please use this identifier to cite or link to this item: http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3829
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dc.creatorTortosa, Ramón-
dc.creatorAceituno, Antonio-
dc.creatorRosa, José M. de la-
dc.creatorRodríguez-Vázquez, Ángel-
dc.creatorFernández, Francisco V.-
dc.date2008-04-28T15:10:20Z-
dc.date2008-04-28T15:10:20Z-
dc.date2007-05-
dc.date.accessioned2017-01-31T01:05:19Z-
dc.date.available2017-01-31T01:05:19Z-
dc.identifierR. Tortosa-Navas,A. Aceituno, J. M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: "A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator". Proceeding of the 2007 International Symposium on Circuits and Systems (ISCAS), New Orleans, May 2007.-
dc.identifier1-4244-0921-7/07-
dc.identifierhttp://hdl.handle.net/10261/3829-
dc.identifier.urihttp://dspace.mediu.edu.my:8181/xmlui/handle/10261/3829-
dc.descriptionThis paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade ΣΔ modulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by a second-order stage, both realized using Gm-C integrators and a 4-bit internal quantizer. Dynamic element matching is included to compensate for the non-linearity of the feedback digital-to-analog converters. The estimated power consumption is 70 mW from a 1.2-V supply voltage when is clocked at 240MHz. CADENCE-SPECTRE simulations show 12-bit effective resolution within a 20-MHz signal bandwidth.-
dc.descriptionThis work has been supported by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under contract TEC2004-01752/MIC.-
dc.descriptionPeer reviewed-
dc.format653200 bytes-
dc.formatapplication/pdf-
dc.languageeng-
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.rightsopenAccess-
dc.subjectContinuous-Time Circuits-
dc.subjectSigma-Delta Modulators-
dc.titleA 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator-
dc.typeArtículo-
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