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http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3841Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.creator | Río, Rocío del | - |
| dc.creator | Medeiro, Fernando | - |
| dc.creator | Rosa, José M. de la | - |
| dc.creator | Pérez-Verdú, Belén | - |
| dc.creator | Rodríguez-Vázquez, Ángel | - |
| dc.date | 2008-04-29T05:32:52Z | - |
| dc.date | 2008-04-29T05:32:52Z | - |
| dc.date | 2000-11 | - |
| dc.date.accessioned | 2017-01-31T01:05:35Z | - |
| dc.date.available | 2017-01-31T01:05:35Z | - |
| dc.identifier | In "CMOS 0.35-um Digital Technology Multi-Bit Cascade Sigma-Delta Modulator in CMOS 0.35μm Digital Technology”. Proc. of the XV Design of Circuits and Integrated Systems Conference, pp. 133-138, Montpellier (France), November 2000. | - |
| dc.identifier | http://hdl.handle.net/10261/3841 | - |
| dc.identifier.uri | http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3841 | - |
| dc.description | This paper presents a 4th-order 3-stage cascade SD modulator that achieves 14-bit dynamic range at 4MS/s using low oversampling ratio. It includes a programmable multi-bit quantizer in the last stage, providing 2-, 3-, or 4-bit internal resolution. The modulator is implemented with fully-differential switched capacitor circuits in a CMOS 0.35-um digital technology. The estimated power consumption is 78mW, from a 3.3-V supply. | - |
| dc.description | This work has been partially supported by the ESPRIT Project 29261 and the CICYT Project TIC 97-0580. | - |
| dc.description | Peer reviewed | - |
| dc.format | 164388 bytes | - |
| dc.format | application/pdf | - |
| dc.language | eng | - |
| dc.rights | openAccess | - |
| dc.subject | Analog-to-Digital Converters | - |
| dc.subject | Sigma-Delta Modulators | - |
| dc.title | A 14-bit 4-MS/s Multi-bit Cascade Sigma-Delta Modulator in CMOS 0.35-um Digital Technology | - |
| dc.type | Artículo | - |
| Appears in Collections: | Digital Csic | |
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