Simulation-based High-level Synthesis of Pipeline Analog-to-Digital Converters

Please use this identifier to cite or link to this item: http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3843

Title:	Simulation-based High-level Synthesis of Pipeline Analog-to-Digital Converters
Keywords:	Pipeline Analog-to-Digital Converters High-level Synthesis
Description:	This paper presents a toolbox for the time-domain simulation and optimization-based high-level synthesis of pipeline analog-to-digital converters in MATLAB®. Behavioral models of building blocks, including their critical error mechanisms, are described and incorporated into SIMULINK® as C-compiled S-functions. This approach significantly speeds up system-level simulations while keeping high accuracy −verified with HSPICE− and interoperability of different subcircuit models. Moreover, their combined use with an efficient optimizer makes the proposed toolbox a valuable alternative for the design of broadband communication analog front-ends. As a case study, an embedded 0.13μm CMOS 12bit@80MS/s ADC for a PLC chipset is designed to show the capabilities of the presented tool. This work has been supported by the MEDEA+ (A110 MIDAS) Project. Peer reviewed
URI:	http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3843
Other Identifiers:	J. Ruiz-Amaya, J.M. de la Rosa and M. Delgado-Restituto: "Simulation-based High-level Synthesis of Pipeline Analog-to-Digital Converters", Proceeding of the 2004 Conference on Design of Circuits and Integrated Systems, pp. 39-44, Bordeaux, November 2004. 2-9522971-0-X http://hdl.handle.net/10261/3843
Appears in Collections:	Digital Csic

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