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http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3846| Title: | Effect of Clock Jitter Error on the Performance Degradation of Multi-bit Continuous-Time ΣΔ Modulators With NRZ DAC |
| Keywords: | Clock jitter Continuous-Time Circuits |
| Description: | This paper analyses the effect of the clock
jitter error in multi-bit continuous-time ΣΔ modulators with non-return-to-zero feedback waveform. Derived expressions show that the jitter-induced noise power can be separated into two main components: one that depends on the modulator loop filter transfer function and the other one due to the input signal parameters, i.e
amplitude and frequency. The latter component, not considered in previous approaches, allows us to accurately predict the resolution loss caused by jitter, showing effects not taken into account up to now in literature which are
specially critical in broadband telecom applications. Moreover, the use of state-space formulation makes the analysis quite general and applicable to either cascade or single-loop architectures. Time-domain simulations of
several modulator topologies intended for VDSL application are given to validate the presented analysis. This work has been supported by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under contracts TEC2004-01752/MIC and TIC2003-02355. Peer reviewed |
| URI: | http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3846 |
| Other Identifiers: | R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: "Effect of Clock Jitter Error on the Performance Degradation of Multi-bit Continuous-Time ΣΔ Modulators with NRZ DAC". Proceeding of the 2005 Conference on Design of Circuits and Integrated Systems, Lisbon, November 2005. http://hdl.handle.net/10261/3846 |
| Appears in Collections: | Digital Csic |
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