Please use this identifier to cite or link to this item:
http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3852| Title: | Reliable analysis of settling errors in SC integrators - application to high-speed low-power ΣΔ modulators design |
| Keywords: | Switched-capacitor circuits Σ-Δ modulators |
| Description: | Comunicación presentada al "XIV Design of Circuits and Integrated Systems Conference" celebrado en Palma de Mallorca (Spain) en Noviembre de 1999. This paper presents a detailed study on the transient response of SC integrators taking into account the effects of amplifier finite gain-bandwidth product and slew-rate during, unlike previous models, both the integration and sampling phases. Results are applied to the design of high-speed low-power ΣΔ modulators and simplified equations are obtained for manual-estimation of the settling error power. This work has been partially supported by the ESPRIT Project 29261 and the CICYT Project TIC 97-0580. Peer reviewed |
| URI: | http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3852 |
| Other Identifiers: | Proceedings of the XIV Design of Circuits and Integrated Systems Conference: 727-732 (1999) http://hdl.handle.net/10261/3852 |
| Appears in Collections: | Digital Csic |
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.