A Multiprocessor Architecture Using Modular Arithmetic for Very High Precision Computation

Please use this identifier to cite or link to this item: http://dspace.mediu.edu.my:8181/xmlui/handle/1721.1/6021

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DC Field	Value	Language
dc.creator	Wu, Henry M.	-
dc.date	2004-10-04T14:36:07Z	-
dc.date	2004-10-04T14:36:07Z	-
dc.date	1989-04-01	-
dc.date.accessioned	2013-10-09T02:42:26Z	-
dc.date.available	2013-10-09T02:42:26Z	-
dc.date.issued	2013-10-09	-
dc.identifier	AIM-1119	-
dc.identifier	http://hdl.handle.net/1721.1/6021	-
dc.identifier.uri	http://koha.mediu.edu.my:8181/xmlui/handle/1721	-
dc.description	We outline a multiprocessor architecture that uses modular arithmetic to implement numerical computation with 900 bits of intermediate precision. A proposed prototype, to be implemented with off-the-shelf parts, will perform high-precision arithmetic as fast as some workstations and mini- computers can perform IEEE double-precision arithmetic. We discuss how the structure of modular arithmetic conveniently maps into a simple, pipelined multiprocessor architecture. We present techniques we developed to overcome a few classical drawbacks of modular arithmetic. Our architecture is suitable to and essential for the study of chaotic dynamical systems.	-
dc.format	12 p.	-
dc.format	2230694 bytes	-
dc.format	827297 bytes	-
dc.format	application/postscript	-
dc.format	application/pdf	-
dc.language	en_US	-
dc.relation	AIM-1119	-
dc.subject	modular arithmetic	-
dc.subject	computer architecture	-
dc.subject	multiprocessor	-
dc.subject	sresidue number system	-
dc.subject	computer arithmetic	-
dc.subject	pipelining	-
dc.subject	chaos	-
dc.title	A Multiprocessor Architecture Using Modular Arithmetic for Very High Precision Computation	-
Appears in Collections:	MIT Items

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