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http://dspace.mediu.edu.my:8181/xmlui/handle/1721.1/6021| Title: | A Multiprocessor Architecture Using Modular Arithmetic for Very High Precision Computation |
| Keywords: | modular arithmetic computer architecture multiprocessor sresidue number system computer arithmetic pipelining chaos |
| Issue Date: | 9-Oct-2013 |
| Description: | We outline a multiprocessor architecture that uses modular arithmetic to implement numerical computation with 900 bits of intermediate precision. A proposed prototype, to be implemented with off-the-shelf parts, will perform high-precision arithmetic as fast as some workstations and mini- computers can perform IEEE double-precision arithmetic. We discuss how the structure of modular arithmetic conveniently maps into a simple, pipelined multiprocessor architecture. We present techniques we developed to overcome a few classical drawbacks of modular arithmetic. Our architecture is suitable to and essential for the study of chaotic dynamical systems. |
| URI: | http://koha.mediu.edu.my:8181/xmlui/handle/1721 |
| Other Identifiers: | AIM-1119 http://hdl.handle.net/1721.1/6021 |
| Appears in Collections: | MIT Items |
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