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http://dspace.mediu.edu.my:8181/xmlui/handle/1721.1/6636Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.creator | Fillo, Marco | - |
| dc.creator | Keckler, Stephen W. | - |
| dc.creator | Dally, William J. | - |
| dc.creator | Carter, Nicholas P. | - |
| dc.creator | Chang, Andrew | - |
| dc.creator | Gurevich, Yevgeny | - |
| dc.creator | Lee, Whay S. | - |
| dc.date | 2004-10-08T20:35:59Z | - |
| dc.date | 2004-10-08T20:35:59Z | - |
| dc.date | 1995-03-01 | - |
| dc.date.accessioned | 2013-10-09T02:46:20Z | - |
| dc.date.available | 2013-10-09T02:46:20Z | - |
| dc.date.issued | 2013-10-09 | - |
| dc.identifier | AIM-1532 | - |
| dc.identifier | http://hdl.handle.net/1721.1/6636 | - |
| dc.identifier.uri | http://koha.mediu.edu.my:8181/xmlui/handle/1721 | - |
| dc.description | The M-Machine is an experimental multicomputer being developed to test architectural concepts motivated by the constraints of modern semiconductor technology and the demands of programming systems. The M- Machine computing nodes are connected with a 3-D mesh network; each node is a multithreaded processor incorporating 12 function units, on-chip cache, and local memory. The multiple function units are used to exploit both instruction-level and thread-level parallelism. A user accessible message passing system yields fast communication and synchronization between nodes. Rapid access to remote memory is provided transparently to the user with a combination of hardware and software mechanisms. This paper presents the architecture of the M-Machine and describes how its mechanisms maximize both single thread performance and overall system throughput. | - |
| dc.format | 393487 bytes | - |
| dc.format | 284613 bytes | - |
| dc.format | application/postscript | - |
| dc.format | application/pdf | - |
| dc.language | en_US | - |
| dc.relation | AIM-1532 | - |
| dc.title | The M-Machine Multicomputer | - |
| Appears in Collections: | MIT Items | |
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