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http://dspace.mediu.edu.my:8181/xmlui/handle/1721.1/6810| Title: | A Parallel Crossbar Routing Chip for a Shared Memory Multiprocessor |
| Keywords: | parallel processing multistage routing network computersarchitecture |
| Issue Date: | 9-Oct-2013 |
| Description: | This thesis describes the design and implementation of an integrated circuit and associated packaging to be used as the building block for the data routing network of a large scale shared memory multiprocessor system. A general purpose multiprocessor depends on high-bandwidth, low-latency communications between computing elements. This thesis describes the design and construction of RN1, a novel self-routing, enhanced crossbar switch as a CMOS VLSI chip. This chip provides the basic building block for a scalable pipelined routing network with byte-wide data channels. A series of RN1 chips can be cascaded with no additional internal network components to form a multistage fault-tolerant routing switch. The chip is designed to operate at clock frequencies up to 100Mhz using Hewlett-Packard's HP34 $1.2\\mu$ process. This aggressive performance goal demands that special attention be paid to optimization of the logic architecture and circuit design. |
| URI: | http://koha.mediu.edu.my:8181/xmlui/handle/1721 |
| Other Identifiers: | AITR-1284 http://hdl.handle.net/1721.1/6810 |
| Appears in Collections: | MIT Items |
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