Please use this identifier to cite or link to this item: http://dspace.mediu.edu.my:8181/xmlui/handle/1721.1/6810
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dc.creatorMinsky, Henry-
dc.date2004-10-20T19:57:43Z-
dc.date2004-10-20T19:57:43Z-
dc.date1991-03-01-
dc.date.accessioned2013-10-09T02:47:00Z-
dc.date.available2013-10-09T02:47:00Z-
dc.date.issued2013-10-09-
dc.identifierAITR-1284-
dc.identifierhttp://hdl.handle.net/1721.1/6810-
dc.identifier.urihttp://koha.mediu.edu.my:8181/xmlui/handle/1721-
dc.descriptionThis thesis describes the design and implementation of an integrated circuit and associated packaging to be used as the building block for the data routing network of a large scale shared memory multiprocessor system. A general purpose multiprocessor depends on high-bandwidth, low-latency communications between computing elements. This thesis describes the design and construction of RN1, a novel self-routing, enhanced crossbar switch as a CMOS VLSI chip. This chip provides the basic building block for a scalable pipelined routing network with byte-wide data channels. A series of RN1 chips can be cascaded with no additional internal network components to form a multistage fault-tolerant routing switch. The chip is designed to operate at clock frequencies up to 100Mhz using Hewlett-Packard's HP34 $1.2\\mu$ process. This aggressive performance goal demands that special attention be paid to optimization of the logic architecture and circuit design.-
dc.format114 p.-
dc.format11927286 bytes-
dc.format4341163 bytes-
dc.formatapplication/postscript-
dc.formatapplication/pdf-
dc.languageen_US-
dc.relationAITR-1284-
dc.subjectparallel processing-
dc.subjectmultistage routing network-
dc.subjectcomputersarchitecture-
dc.titleA Parallel Crossbar Routing Chip for a Shared Memory Multiprocessor-
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