Performance Evaluation of the Scheme 86 and HP Precision Architecture

Please use this identifier to cite or link to this item: http://dspace.mediu.edu.my:8181/xmlui/handle/1721.1/6978

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DC Field	Value	Language
dc.creator	Wu, Henry M.	-
dc.date	2004-10-20T20:12:01Z	-
dc.date	2004-10-20T20:12:01Z	-
dc.date	1989-04-01	-
dc.date.accessioned	2013-10-09T02:48:01Z	-
dc.date.available	2013-10-09T02:48:01Z	-
dc.date.issued	2013-10-09	-
dc.identifier	AITR-1103	-
dc.identifier	http://hdl.handle.net/1721.1/6978	-
dc.identifier.uri	http://koha.mediu.edu.my:8181/xmlui/handle/1721	-
dc.description	The Scheme86 and the HP Precision Architectures represent different trends in computer processor design. The former uses wide micro-instructions, parallel hardware, and a low latency memory interface. The latter encourages pipelined implementation and visible interlocks. To compare the merits of these approaches, algorithms frequently encountered in numerical and symbolic computation were hand-coded for each architecture. Timings were done in simulators and the results were evaluated to determine the speed of each design. Based on these measurements, conclusions were drawn as to which aspects of each architecture are suitable for a high- performance computer.	-
dc.format	7085809 bytes	-
dc.format	2582214 bytes	-
dc.format	application/postscript	-
dc.format	application/pdf	-
dc.language	en_US	-
dc.relation	AITR-1103	-
dc.title	Performance Evaluation of the Scheme 86 and HP Precision Architecture	-
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