Fat-Tree Routing for Transit

Please use this identifier to cite or link to this item: http://dspace.mediu.edu.my:8181/xmlui/handle/1721.1/7026

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DC Field	Value	Language
dc.creator	DeHon, Andre	-
dc.date	2004-10-20T20:22:45Z	-
dc.date	2004-10-20T20:22:45Z	-
dc.date	1990-02-01	-
dc.date.accessioned	2013-10-09T02:48:02Z	-
dc.date.available	2013-10-09T02:48:02Z	-
dc.date.issued	2013-10-09	-
dc.identifier	AITR-1224	-
dc.identifier	http://hdl.handle.net/1721.1/7026	-
dc.identifier.uri	http://koha.mediu.edu.my:8181/xmlui/handle/1721	-
dc.description	The Transit network provides high-speed, low-latency, fault-tolerant interconnect for high-performance, multiprocessor computers. The basic connection scheme for Transit uses bidelta style, multistage networks to support up to 256 processors. Scaling to larger machines by simply extending the bidelta network topology will result in a uniform degradation of network latency between all processors. By employing a fat-tree network structure in larger systems, the network provides locality and universality properties which can help minimize the impact of scaling on network latency. This report details the topology and construction issues associated with integrating Transit routing technology into fat-tree interconnect topologies.	-
dc.format	4074548 bytes	-
dc.format	3944868 bytes	-
dc.format	application/postscript	-
dc.format	application/pdf	-
dc.language	en_US	-
dc.relation	AITR-1224	-
dc.title	Fat-Tree Routing for Transit	-
Appears in Collections:	MIT Items

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