Please use this identifier to cite or link to this item: http://dspace.mediu.edu.my:8181/xmlui/handle/1957/1202
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dc.contributorFiez, Terri-
dc.contributorCoakley, Jim-
dc.contributorMoon, Un-Ku-
dc.contributorMayaram, Kartikeya-
dc.contributorTemes, Gábor-
dc.date2006-03-06T15:26:02Z-
dc.date2006-03-06T15:26:02Z-
dc.date2006-01-27-
dc.date2006-03-06T15:26:02Z-
dc.date.accessioned2013-10-16T07:33:08Z-
dc.date.available2013-10-16T07:33:08Z-
dc.date.issued2013-10-16-
dc.identifierhttp://hdl.handle.net/1957/1202-
dc.identifier.urihttp://koha.mediu.edu.my:8181/xmlui/handle/1957/1202-
dc.descriptionGraduation date: 2006-
dc.descriptionIn recent years, there has been growing interest in both industry and academia to use continuous-time (CT) Δ-Σ A/D converters for wideband wireless and wireline communication applications. So far no reported CT Δ-Σ A/D modulator achieves 14-bit or higher dynamic range (DR) with more than 2MHz signal bandwidth (equivalently 4MS/s). This dissertation presents the realization of a continuous-time (CT) Δ-Σ A/D modulator providing 80.5dB SNDR and 85dB DR with 5MS/s output data rate in a 2.5V 0.25µm CMOS process. The modulator has a single-stage dual-loop architecture allowing large quantizer delay. A 17-level quantizer is used to increase resolution and non-return-to-zero DACs are adopted to reduce clock jitter sensitivity. Capacitor tuning is utilized to overcome time-constant variation. On-chip self-calibration is implemented to suppress DAC nonlinearity. Combining techniques to address various design challenges, the modulator consumes 50mW with 60MHz sampling rate.-
dc.languageen_US-
dc.subjectdelta sigma-
dc.subjectcontinuous-time-
dc.subjectmodulator-
dc.subjectcalibration-
dc.titleDesign of a 14-bit continuous-time Delta-Sigma A/D modulator with 2.5MHz signal bandwidth-
dc.typeThesis-
Appears in Collections:ScholarsArchive@OSU

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