Low-power design techniques for low-voltage analog-to-digital converters

Please use this identifier to cite or link to this item: http://dspace.mediu.edu.my:8181/xmlui/handle/1957/2054

Title:	Low-power design techniques for low-voltage analog-to-digital converters
Authors:	Moon, Un-Ku Moon, Un-Ku Temes, Gabor Mayaram, Karti Liu, Huaping Coakley, Jim Jr.
Keywords:	low-power low-voltage ADC double-sampling
Issue Date:	16-Oct-2013
Description:	Graduation date: 2006 The demand for portable electronic systems and the continued down-scaling of device dimensions resulted in rapid improvement in the performance of integrated systems. Several low-voltage design techniques have been proposed to operate analog circuits with sub-1V supply. However, these techniques require higher power consumption to achieve large dynamic range while operating with low supply voltage. In this thesis, two low-power design techniques for low-voltage data converters are proposed. The first technique is low-voltage double-sampling method for delta-sigma analog-to-digital converters using a combination of switched-RC technique and floating switched-capacitor configuration. The second technique is an improved clocking scheme for algorithmic analog-to-digital converters with on-chip delay-locked-loop. A 0.9V 92dB delta-sigma audio ADC and a 10MS/s 11-b algorithmic ADC were implemented to demonstrate the proposed design techniques.
URI:	http://koha.mediu.edu.my:8181/xmlui/handle/1957/2054
Other Identifiers:	http://hdl.handle.net/1957/2054
Appears in Collections:	ScholarsArchive@OSU

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