Low power scheduling schemes that consider latency and resource constraints at multiple voltages

Please use this identifier to cite or link to this item: http://dspace.mediu.edu.my:8181/xmlui/handle/1957/2629

Title:	Low power scheduling schemes that consider latency and resource constraints at multiple voltages
Authors:	Wang, Zhongfeng Lawrence, Marple Eugene, Zhang
Keywords:	Low power
Issue Date:	16-Oct-2013
Description:	Graduation date: 2007 Power reduction can be achieved at many different levels, such as architecture, algorithm, logic, and transistor levels in circuit design. This thesis focuses on low power scheduling at the algorithm level. We present a latency-constrained scheduling and a latency and resource constrained scheduling, which minimize power consumption for the resources and registers operating at multiple cycles and voltages. The proposed schemes are based on the consideration of assigning most nodes to low voltage and reducing the number of registers simultaneously. We present a comprehensive scheduling methodology to decrease average power, peak power, and the number of registers during the scheduling stage. To target this goal, we propose the efficient algorithms to schedule DFG with the least power dissipation that satisfies the system constraints in timing and resources. Our benchmark shows that our approach has succeeded to reduce power in 12.99~41.97% in latency-constrained scheduling and 20.19~80.64% in latency and resource constrained scheduling for those multimedia kernels.
URI:	http://koha.mediu.edu.my:8181/xmlui/handle/1957/2629
Other Identifiers:	http://hdl.handle.net/1957/2629
Appears in Collections:	ScholarsArchive@OSU

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