Please use this identifier to cite or link to this item: http://dspace.mediu.edu.my:8181/xmlui/handle/1957/2841
Full metadata record
DC FieldValueLanguage
dc.contributorMoon, Un-Ku-
dc.contributorLevien, Keith-
dc.date2006-08-03T14:42:54Z-
dc.date2006-08-03T14:42:54Z-
dc.date2006-08-03T14:42:54Z-
dc.date.accessioned2013-10-16T07:39:18Z-
dc.date.available2013-10-16T07:39:18Z-
dc.date.issued2013-10-16-
dc.identifierhttp://hdl.handle.net/1957/2841-
dc.identifier.urihttp://koha.mediu.edu.my:8181/xmlui/handle/1957/2841-
dc.descriptionDate presented: 2006-07-21-
dc.descriptionGraduation date: 2007-
dc.descriptionA digital phase locked loop (DPLL) and a statistical time-to-digital converter (STDC) were previously fabricated in a 0.35µm, 3.3V SOI CMOS process. This work summarizes these designs and characterizes the measured performance. Simulations supplement the measurements where applicable. The DPLL was found to reach a locked state under a limited range of input conditions. Evaluation of the DPLL's digitally controlled analog oscillator (DCAO) revealed that transistor mismatch resulted in a non-ideal tuning curve. Simulations and measurements of the DCAO phase noise showed good correlation. The STDC circuit was characterized for several test chips. Measurement results show good matching between the chips for the same input conditions. The ability to achieve higher resolution than standard time-to-digital converters is demonstrated through simulations and measurements.-
dc.languageen_US-
dc.subjectStochastic Time to Digital Converter-
dc.subjectDigital Phase Locked Loop-
dc.titleCharacterization of a digital phase locked loop and a stochastic time to digital converter-
dc.typeThesis-
Appears in Collections:ScholarsArchive@OSU

Files in This Item:
There are no files associated with this item.


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.