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| DC Field | Value | Language |
|---|---|---|
| dc.contributor | Lee, Ben | - |
| dc.contributor | Traylor, Roger | - |
| dc.contributor | Nguyen, Thinh | - |
| dc.contributor | Savage, Tom | - |
| dc.date | 2006-10-16T15:37:38Z | - |
| dc.date | 2006-10-16T15:37:38Z | - |
| dc.date | 2006-09-29 | - |
| dc.date | 2006-10-16T15:37:38Z | - |
| dc.date.accessioned | 2013-10-16T07:40:59Z | - |
| dc.date.available | 2013-10-16T07:40:59Z | - |
| dc.date.issued | 2013-10-16 | - |
| dc.identifier | http://hdl.handle.net/1957/3143 | - |
| dc.identifier.uri | http://koha.mediu.edu.my:8181/xmlui/handle/1957/3143 | - |
| dc.description | Graduation date: 2007 | - |
| dc.description | Dynamic multithreaded processors attempt to increase the performance of a single sequential program by dynamically extracting threads from sources such as loop iterations. The scheduling of instructions in such a processor plays a vital role in the amount of thread level parallelism that can be extracted and thus the overall system performance. Three new systems are presented in this thesis to increase the performance of instruction scheduling and value forwarding in a dynamic multithreaded processor. Conflicts within the instruction cache from multiple threads requesting the same cache blocks reduces instruction fetch performance. A new instruction scheduling and fetching method is presented that uses the unique nature of dynamically generated threads to increase fetch performance while keeping the complexity of the instruction cache low. Performance for this new fetching scheme is on par or better than the current instruction fetching method used by the simulated processor. The overall performance of a dynamic multithreaded processor is limited by interthread dependencies that arise from generating threads that are not fully independent or parallel. A new inter-thread forwarding system is presented that speeds up the forwarding of values between threads, thus reducing the number of stalls from interthread dependencies. To further reduce the number of stalls, a critical path system is implemented that dynamically identifies and prioritizes instructions that produce interthread dependency values. | - |
| dc.language | en_US | - |
| dc.subject | multithreading | - |
| dc.subject | value forwarding | - |
| dc.subject | dynamic threading | - |
| dc.subject | scheduling | - |
| dc.subject | fetching | - |
| dc.subject | grouping | - |
| dc.subject | critical path | - |
| dc.subject | inter-thread | - |
| dc.title | Instruction fetching, scheduling, and forwarding in a dynamic multithreaded processor | - |
| dc.type | Thesis | - |
| Appears in Collections: | ScholarsArchive@OSU | |
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