Please use this identifier to cite or link to this item:
http://dspace.mediu.edu.my:8181/xmlui/handle/1957/3530| Title: | Design techniques for clocking high performance signaling systems |
| Authors: | Moon, Un-Ku Wei, Gu-Yeon Mayaram, Kartikeya Temes, Gabor Mooney, Randy Yim, Solomon |
| Keywords: | PLL CDR |
| Issue Date: | 16-Oct-2013 |
| Description: | Scaling of CMOS technology has progressed relentlessly for the past several decades. In order for this unprecedented scaling to benefit the performance of large digital systems, the communication bandwidth between integrated circuits (ICs) must scale accordingly. However, interconnect technology does not scale as aggressively, making communication between chips the major bottleneck in overall system performance. In addition, supply voltage scaling, increasing device leakage, and increased noise make existing signaling circuits inefficient and difficult to scale. In this thesis, both analog and digital enhancement techniques to mitigate scaling related issues and improve the performance of building blocks used in high- speed signaling systems are discussed. A digital-to-phase converter (DPC) with a resolution better than 100 femto-second resolution, a hybrid analog/digital clock and data recovery (CDR) architecture that improves the tracking range of tra- ditional CDRs by an order of magnitude, and a digital CDR architecture that obviates the need for the charge pump and the large area occupying loop filter, while achieving error-free operation are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques. |
| URI: | http://koha.mediu.edu.my:8181/xmlui/handle/1957/3530 |
| Other Identifiers: | http://hdl.handle.net/1957/3530 |
| Appears in Collections: | ScholarsArchive@OSU |
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.