Please use this identifier to cite or link to this item: http://dspace.mediu.edu.my:8181/xmlui/handle/1957/465
Title: A MOSCAP pipeline pseudo passive DAC
Authors: Temes, Gabor C
Settaluri, Raghu
Traylor, Roger
Kimura, Shoichi
Keywords: DAC
pipeline
MOSCAP
digital-to-analog
SCF
D/A
Issue Date: 16-Oct-2013
Description: Graduation date: 2006
The design of a 10-bit pipelined charge redistribution DAC employing MOSCAPs biased in their accumulation mode is presented in this thesis. A switched capacitor filter and output buffer have also been designed for the system. The effect of MOSCAP nonlinearity on the performance of the pipelined charge redistribution DAC has been analyzed. MOS capacitors and their models available for simulation have been discussed. In addition, the effect of more general capacitor nonlinearities on the performance of the DAC has been presented.
URI: http://koha.mediu.edu.my:8181/xmlui/handle/1957/465
Other Identifiers: http://hdl.handle.net/1957/465
Appears in Collections:ScholarsArchive@OSU

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