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A fault-tolerant multiprocessor architecture for digital signal processing applications

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dc.contributor Song, William S.
dc.contributor Musicus, Bruce R.
dc.date 2004-03-02T18:30:10Z
dc.date 2004-03-02T18:30:10Z
dc.date 1990
dc.date.accessioned 2013-10-09T02:34:26Z
dc.date.available 2013-10-09T02:34:26Z
dc.date.issued 2013-10-09
dc.identifier No. 503
dc.identifier http://hdl.handle.net/1721.1/4200
dc.identifier.uri http://koha.mediu.edu.my:8181/xmlui/handle/1721
dc.description William S. Song and Bruce R. Musicus.
dc.description Also issued as Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1989.
dc.description Includes bibliographical references (p. 141-143).
dc.description Supported in part by U.S. Air Force Office of Scientific Research. AFOSR 86-0164 Supported in part by Charles S. Draper Laborarory. DL-H-404158
dc.format 143 p.
dc.format 12929925 bytes
dc.format application/pdf
dc.language eng
dc.publisher Massachusetts Institute of Technology, Research Laboratory of Electronics
dc.relation Technical report (Massachusetts Institute of Technology. Research Laboratory of Electronics) ; 552.
dc.subject TK7855.M41 R43 no.552
dc.title A fault-tolerant multiprocessor architecture for digital signal processing applications


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