Scheme 86: An Architecture for Microcoding a Scheme Interpreter

dc.creator	Wu, Henry M.
dc.date	2004-10-04T14:57:27Z
dc.date	2004-10-04T14:57:27Z
dc.date	1988-08-01
dc.date.accessioned	2013-10-09T02:45:35Z
dc.date.available	2013-10-09T02:45:35Z
dc.date.issued	2013-10-09
dc.identifier	AIM-953
dc.identifier	http://hdl.handle.net/1721.1/6468
dc.identifier.uri	http://koha.mediu.edu.my:8181/xmlui/handle/1721
dc.description	I describe the design and implementation plans for a computer that is optimized as a microcoded interpreter for Scheme. The computer executes SCode, a typed-pointer representation. The memory system has low-latency as well as high throughput. Multiple execution units in the processor complete complex operations in less than one memory cycle, allowing efficient use of memory bandwidth. The processor provides hardware support for tagged data objects and runtime type checking. I will discuss the motivation for this machine, its architecture, why it can interpret Scheme efficiently, and the computer-aided design tools developed for building this computer.
dc.format	8410321 bytes
dc.format	3025225 bytes
dc.format	application/postscript
dc.format	application/pdf
dc.language	en_US
dc.relation	AIM-953
dc.title	Scheme 86: An Architecture for Microcoding a Scheme Interpreter

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