| dc.creator |
Minsky, Henry |
|
| dc.date |
2004-10-20T19:57:43Z |
|
| dc.date |
2004-10-20T19:57:43Z |
|
| dc.date |
1991-03-01 |
|
| dc.date.accessioned |
2013-10-09T02:47:00Z |
|
| dc.date.available |
2013-10-09T02:47:00Z |
|
| dc.date.issued |
2013-10-09 |
|
| dc.identifier |
AITR-1284 |
|
| dc.identifier |
http://hdl.handle.net/1721.1/6810 |
|
| dc.identifier.uri |
http://koha.mediu.edu.my:8181/xmlui/handle/1721 |
|
| dc.description |
This thesis describes the design and implementation of an integrated circuit and associated packaging to be used as the building block for the data routing network of a large scale shared memory multiprocessor system. A general purpose multiprocessor depends on high-bandwidth, low-latency communications between computing elements. This thesis describes the design and construction of RN1, a novel self-routing, enhanced crossbar switch as a CMOS VLSI chip. This chip provides the basic building block for a scalable pipelined routing network with byte-wide data channels. A series of RN1 chips can be cascaded with no additional internal network components to form a multistage fault-tolerant routing switch. The chip is designed to operate at clock frequencies up to 100Mhz using Hewlett-Packard's HP34 $1.2\\mu$ process. This aggressive performance goal demands that special attention be paid to optimization of the logic architecture and circuit design. |
|
| dc.format |
114 p. |
|
| dc.format |
11927286 bytes |
|
| dc.format |
4341163 bytes |
|
| dc.format |
application/postscript |
|
| dc.format |
application/pdf |
|
| dc.language |
en_US |
|
| dc.relation |
AITR-1284 |
|
| dc.subject |
parallel processing |
|
| dc.subject |
multistage routing network |
|
| dc.subject |
computersarchitecture |
|
| dc.title |
A Parallel Crossbar Routing Chip for a Shared Memory Multiprocessor |
|