المستودع الأكاديمي جامعة المدينة

Design of a 14-bit continuous-time Delta-Sigma A/D modulator with 2.5MHz signal bandwidth

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dc.contributor Fiez, Terri
dc.contributor Coakley, Jim
dc.contributor Moon, Un-Ku
dc.contributor Mayaram, Kartikeya
dc.contributor Temes, Gábor
dc.date 2006-03-06T15:26:02Z
dc.date 2006-03-06T15:26:02Z
dc.date 2006-01-27
dc.date 2006-03-06T15:26:02Z
dc.date.accessioned 2013-10-16T07:33:08Z
dc.date.available 2013-10-16T07:33:08Z
dc.date.issued 2013-10-16
dc.identifier http://hdl.handle.net/1957/1202
dc.identifier.uri http://koha.mediu.edu.my:8181/xmlui/handle/1957/1202
dc.description Graduation date: 2006
dc.description In recent years, there has been growing interest in both industry and academia to use continuous-time (CT) Δ-Σ A/D converters for wideband wireless and wireline communication applications. So far no reported CT Δ-Σ A/D modulator achieves 14-bit or higher dynamic range (DR) with more than 2MHz signal bandwidth (equivalently 4MS/s). This dissertation presents the realization of a continuous-time (CT) Δ-Σ A/D modulator providing 80.5dB SNDR and 85dB DR with 5MS/s output data rate in a 2.5V 0.25µm CMOS process. The modulator has a single-stage dual-loop architecture allowing large quantizer delay. A 17-level quantizer is used to increase resolution and non-return-to-zero DACs are adopted to reduce clock jitter sensitivity. Capacitor tuning is utilized to overcome time-constant variation. On-chip self-calibration is implemented to suppress DAC nonlinearity. Combining techniques to address various design challenges, the modulator consumes 50mW with 60MHz sampling rate.
dc.language en_US
dc.subject delta sigma
dc.subject continuous-time
dc.subject modulator
dc.subject calibration
dc.title Design of a 14-bit continuous-time Delta-Sigma A/D modulator with 2.5MHz signal bandwidth
dc.type Thesis


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