| dc.contributor | Moon, Un-Ku | |
| dc.contributor | Moon, Un-Ku | |
| dc.contributor | Temes, Gabor | |
| dc.contributor | Mayaram, Karti | |
| dc.contributor | Liu, Huaping | |
| dc.contributor | Coakley, Jim Jr. | |
| dc.date | 2006-05-31T23:16:28Z | |
| dc.date | 2006-05-31T23:16:28Z | |
| dc.date | 2006-05-04 | |
| dc.date | 2006-05-31T23:16:28Z | |
| dc.date.accessioned | 2013-10-16T07:36:12Z | |
| dc.date.available | 2013-10-16T07:36:12Z | |
| dc.date.issued | 2013-10-16 | |
| dc.identifier | http://hdl.handle.net/1957/2054 | |
| dc.identifier.uri | http://koha.mediu.edu.my:8181/xmlui/handle/1957/2054 | |
| dc.description | Graduation date: 2006 | |
| dc.description | The demand for portable electronic systems and the continued down-scaling of device dimensions resulted in rapid improvement in the performance of integrated systems. Several low-voltage design techniques have been proposed to operate analog circuits with sub-1V supply. However, these techniques require higher power consumption to achieve large dynamic range while operating with low supply voltage. In this thesis, two low-power design techniques for low-voltage data converters are proposed. The first technique is low-voltage double-sampling method for delta-sigma analog-to-digital converters using a combination of switched-RC technique and floating switched-capacitor configuration. The second technique is an improved clocking scheme for algorithmic analog-to-digital converters with on-chip delay-locked-loop. A 0.9V 92dB delta-sigma audio ADC and a 10MS/s 11-b algorithmic ADC were implemented to demonstrate the proposed design techniques. | |
| dc.language | en_US | |
| dc.subject | low-power | |
| dc.subject | low-voltage | |
| dc.subject | ADC | |
| dc.subject | double-sampling | |
| dc.title | Low-power design techniques for low-voltage analog-to-digital converters | |
| dc.type | Thesis |
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