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As the functionality of digital chips continues to increase dramatically, chip-
to-chip communication bandwidths must scale accordingly to avoid constraining
the overall system performance. Therefore, high speed transceiver design has be-
come an important research topic. In particular, the performance of the circuits
that are responsible for timing accuracy are important as bit periods continue
to shrink. Furthermore, in order for these circuits to have a true impact on the
performance of the system, they must use unique architectures to achieve timing
accuracy rather than simply trading power consumption for performance.
This thesis discusses issues related to the timing circuits on both the transmit
and receive side of the link. On the transmit side, a phase-locked loop (PLL) is
used to generate the clock that tells the driver when to start and stop driving the
current bit onto the channel. On the receive side, a clock and data recovery (CDR)
circuit is responsible for properly centering the sampling clock in the middle of
the bit period. Design techniques to achieve good timing performance in both the
PLL and CDR are proposed. Specifically, the PLL incorporates a supply regulated
tuning scheme to combat the high levels of supply noise present in large digital
chips and a resistor-based charge pump to reduce the charge pump flicker noise
contribution. The CDR uses oversampling to decouple the tradeoff between two
important performance metrics: jitter generation and jitter tolerance.
To validate the proposed ideas, both a PLL test chip and a CDR test chip
are presented. The PLL operates from 0.5GHz to 2.5GHz and achieves 2.36ps
rms jitter using a ring voltage-controlled oscillator. The power consumption scales
favorably with frequency, using much less power at lower frequencies where less
power is needed. The CDR operates up to 3.6Gbps with a BER of less than 10[superscript -12].
The measured jitter tolerance corner frequency was improved by a factor of 30
from 1MHz to 30MHz without increasing the recovered clock jitter. |
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