| dc.contributor | Fiez, Terri S | |
| dc.contributor | Mayaram, Kartikeya | |
| dc.contributor | Liu, Huaping | |
| dc.contributor | Hetherington, William | |
| dc.date | 2007-01-29T22:29:57Z | |
| dc.date | 2007-01-29T22:29:57Z | |
| dc.date | 2006-12-14 | |
| dc.date | 2007-01-29T22:29:57Z | |
| dc.date.accessioned | 2013-10-16T07:44:18Z | |
| dc.date.available | 2013-10-16T07:44:18Z | |
| dc.date.issued | 2013-10-16 | |
| dc.identifier | http://hdl.handle.net/1957/3874 | |
| dc.identifier.uri | http://koha.mediu.edu.my:8181/xmlui/handle/1957/3874 | |
| dc.description | Graduation date: 2007 | |
| dc.description | Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL Convention Logic (NCL) and traditional Clocked Boolean Logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 um process shows that a pseudo-random number generator implemented with NCL generates 23 dB less substrate noise compared to the equivalent synchronous design. In a larger scale digital circuit, the substrate noise improvement offered by an asynchronous 8051 processor over its synchronous counterpart was nearly 10 dB. The effect of this substrate noise on an analog circuit was explored with a delta sigma modulator (DSM) example. The SNR performance of a second order DSM was not affected by the substrate noise from the NCL 8051 processor while it experiences up to 15 dB degradation when the CBL 8051 processor is clocked near integer multiples of the DSM sampling frequency. | |
| dc.language | en_US | |
| dc.subject | substrate noise | |
| dc.subject | synchronous circuit | |
| dc.subject | asynchronous circuit | |
| dc.subject | null convention logic | |
| dc.subject | delta sigma modulator | |
| dc.title | Comparison and impact of substrate noise due to clocked and clockless circuitry | |
| dc.type | Thesis |
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