| dc.description |
To realize pipelined ADCs in deep-submicron processes, low voltage techniques
must be developed to work around problems created by limited supply voltages such as
the floating switch dead zone, reduced SNR, and reduced OpAmp performance.
This thesis analyzes standard and low voltage design issues for pipelined ADCs
and proposes a fully-differential implementation of the OpAmp Reset Switching
Technique (ORST) as a suitable low voltage design solution. The technique uses a true
fully differential MDAC structure with a switching common-mode feedback to achieve
increased linearity and noise performance over the previously published ORST.
A pipelined ADC test chip is designed to implement the fully differential ORST
technique as a proof of concept. The design also includes a simple, low power input
sampling network that also allows an increased input signal range and saves power by
removing the dedicated, front-end S/H.
Prototype performance demonstrates the fully differential ORST and shows
sampling speeds of up to 60 MS/s, 51.4 dB SNR, 58.8 dB SFDR, and 49.7 dB SNDR for
an 8-bit ENOB in a 0.18 μm CMOS process with a 1 V supply. Little change in distortion
is observed up to 90 MHz input frequency, demonstrating operation without a S/H. |
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