Design techniques for radiation hardened-phase locked loops

dc.contributor	Mayaram, Kartikeya
dc.contributor	Moon, Un-Ku
dc.contributor	Jander, Albrecht
dc.contributor	Kimura, Shoichi
dc.date	2005-09-13T20:38:28Z
dc.date	2005-09-13T20:38:28Z
dc.date	2005-08-23
dc.date	2005-09-13T20:38:28Z
dc.date.accessioned	2013-10-16T07:27:14Z
dc.date.available	2013-10-16T07:27:14Z
dc.date.issued	2013-10-16
dc.identifier	http://hdl.handle.net/1957/445
dc.identifier.uri	http://koha.mediu.edu.my:8181/xmlui/handle/1957/445
dc.description	Graduation date: 2006
dc.description	Spacecrafts experience radiation in the course of their operation and all electronic equipment on board these spacecrafts has to be designed to withstand the effects of this radiation. This thesis describes the effects of total ionization dose (TID) and single event transients (SET) in phase-locked loops - an important circuit block for communication circuits and clock generation. The design of a digital phase-locked loop made tolerant to SET through redundancy and error correction techniques has been described. Digital phase-locked loops can also incorporate self-calibration techniques to compensate for the effects of TID. A linear analysis is presented for the design of digital phase-locked loops. This digital phase-locked loop was fabricated in the Honeywell 0.35 μm SOI CMOS process.
dc.language	en_US
dc.subject	Radiation hardened
dc.subject	Phase-locked loops
dc.title	Design techniques for radiation hardened-phase locked loops
dc.type	Thesis

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