| dc.contributor |
Moon, Un-Ku |
|
| dc.contributor |
Mayaram, Kartikeya |
|
| dc.contributor |
Dhagat, Pallavi |
|
| dc.date |
2005-09-28T23:19:41Z |
|
| dc.date |
2005-09-28T23:19:41Z |
|
| dc.date |
2005-08-26 |
|
| dc.date |
2005-09-28T23:19:41Z |
|
| dc.date.accessioned |
2013-10-16T07:27:19Z |
|
| dc.date.available |
2013-10-16T07:27:19Z |
|
| dc.date.issued |
2013-10-16 |
|
| dc.identifier |
http://hdl.handle.net/1957/482 |
|
| dc.identifier.uri |
http://koha.mediu.edu.my:8181/xmlui/handle/1957/482 |
|
| dc.description |
Graduation date: 2006 |
|
| dc.description |
Digital phase-locked loops (PLLs) have been receiving increasing attention recently due to their ease of integration, scalability and performance comparable to their analog counterparts. In digital PLLs, increased resolution in time-to-digital conversion is desirable for improved noise performance. This work describes the design and simulation of a stochastic time-to-digital converter (STDC) for a digital PLL to attain high resolution. The converter is intended to comprise the fine loop of the phase-frequency detector, whose coarse loop would be comprised of a time-to-digital converter designed using the conventional delay-chain approach. The STDC is designed, simulated and sent for fabrication in a 0.35μm SOI CMOS process. System level simulations in MATLAB are verified by device level simulations in Spectre on circuits extracted from layout. The results support the viability of using the proposed circuit for high resolution time-to-digital conversion. |
|
| dc.language |
en_US |
|
| dc.subject |
time-to-digital converter |
|
| dc.subject |
dpll |
|
| dc.title |
A stochastic time-to-digital converter for digital phase-locked loops |
|
| dc.type |
Thesis |
|